Field plates of various constructions have been embedded within semiconductor devices to effectively reduce the peak electric field at a given voltage, or equivalently to increase the breakdown voltage where the critical electric field is reached. Such field plates have been used for various devices, including LDMOS (Lateral Diffused Metal-Oxide-Semiconductor) transistors. FIG. 1 is a schematically depicted plan view of various portions of a traditional LDMOS device 00. The LDMOS device 00 comprises a field plate contact 01 above a field plate (not shown) and a field plate contact metal layer 02 positioned above the field plate contact 01. The field plate contact 02 is in parallel with a drain contact 02 in the longitudinal direction. A drain contact metal layer 04 is positioned above the drain contact 03. The field plate contact 01 comprises two edges E1 and E2 in the lateral direction and the field plate contact metal layer 02 extends from one edge E1 to the other edge E2 of the field plate contact 01 for realizing the electrical connectivity between the field plate contact 01 and an external applying voltage.
One issue with the above configuration is that the parallel field plate contact metal layer 02 and drain contact metal layer 04 generate fringing fields which result parasitic capacitances therebetween and thus causes associated power loss and efficiency reduction for the switching operation of the LDMOS device.
Thus, an LDMOS device with a configuration that at least addresses the above issue is desired.